Here are a couple of personal and non-commercial FPGA projects. Lots of fun for both of them! The first one below (2013) is a result of a week-long workshop at the University of Cambridge that I have done together with a smart bunch of academics from Universities around the world. During that time I was personally interested in High Performance Computing, High Frequency Trading and other low latency applications on FPGAs and I had come across the NetFPGA open Hardware platform originated by Standford University and developed in collaboration with the University of Cambridge. I had been avidly researching for a way to get my hands on the 10G NetFPGA and when the opportunity of this academic workshop came about I jumped on it! It went really well, so well that I even won the prize for the best project! What an honour!
The earlier project (2007) is another fun one (especially because I got to play with audio), developed during University in Pisa.
2-6 Sept 2013: Pre-trade Position Monitor on 10G NetFPGA
NetFPGA European Summer Camp 2013 @ University of Cambridge
The project has won the prize for the best project of the Camp.
Team work: 3 people.
CADs: Xilinx ISE Design Suite (XPS, ISim, XST, Impact, …)
Language: Verilog, Python, bash, C
Keywords: Low Latency Trading, NetFPGA, NIC, PCIe, Ethernet, Pre-trade Risk Position Monitor, IP packets, scapy, AXI bus, Microblaze.
– Design of a low latency pre-trade risk position monitor implemented on 10G NetFPGA. The NetFPGA board (installed in a host computer) receives orders (coded using a simple ASCII code) from a Server via Ethernet and forwards them to a client. The Logic implemented is able to inspect the payload of the packets, decode the orders, calculate the positions for each of the traded instruments and set up alarms when the limits (set from the host via PCIe) are breached. Extra-checks on the DST IP are performed. Simple GUIs for human interactions have been created at the Server side for sending orders and on the host in order to configure the monitor (limits, destination IPs, etc can be set interactively) and display in real time the trading positions (via PCIe).
2007: Design and realization of a system for audio signal conversion and FIR filtering on Altera Cyclone FPGA
Team work: 2 people.
CADs: Altera Quartus II, OrCAD (Capture, PSpice, Layout).
Language: AHDL
Keywords: Altera UP3 Board, Altera Cyclone FPGA, Audio Signals, ADC and DAC, PCB Design and Realisation.
User Manual in pdf [Italian]
Report Document in pdf [Italian]